Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
u0|rst_controller_002|alt_rst_req_sync_uq1 2 1 0 1 1 1 1 1 0 0 0 0 0
u0|rst_controller_002|alt_rst_sync_uq1 2 0 0 0 1 0 0 0 0 0 0 0 0
u0|rst_controller_002 33 31 0 31 1 31 31 31 0 0 0 0 0
u0|rst_controller_001|alt_rst_req_sync_uq1 2 1 0 1 1 1 1 1 0 0 0 0 0
u0|rst_controller_001|alt_rst_sync_uq1 2 0 0 0 1 0 0 0 0 0 0 0 0
u0|rst_controller_001 33 30 0 30 2 30 30 30 0 0 0 0 0
u0|rst_controller|alt_rst_req_sync_uq1 2 1 0 1 1 1 1 1 0 0 0 0 0
u0|rst_controller|alt_rst_sync_uq1 2 0 0 0 1 0 0 0 0 0 0 0 0
u0|rst_controller 33 31 0 31 2 31 31 31 0 0 0 0 0
u0|irq_synchronizer_001 5 0 2 0 1 0 0 0 0 0 0 0 0
u0|irq_synchronizer 5 0 2 0 1 0 0 0 0 0 0 0 0
u0|irq_mapper 6 28 2 28 32 28 28 28 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_011|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_011 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_010|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_010 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_009|error_adapter_0 22 1 2 1 21 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_009 22 0 0 0 21 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_008|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_008 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_007|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_007 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_006|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_006 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_005|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_005 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_004|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_004 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_003|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_003 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_002|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_002 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_001|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter_001 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|avalon_st_adapter 38 0 0 0 37 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_007|clock_xer|out_to_in_synchronizer 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_007|clock_xer|in_to_out_synchronizer 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_007|clock_xer 125 0 0 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_007 127 2 0 2 121 2 2 2 0 0 0 0 0
u0|mm_interconnect_0|crosser_006|clock_xer|out_to_in_synchronizer 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_006|clock_xer|in_to_out_synchronizer 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_006|clock_xer 125 0 0 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_006 127 2 0 2 121 2 2 2 0 0 0 0 0
u0|mm_interconnect_0|crosser_005|clock_xer|out_to_in_synchronizer 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_005|clock_xer|in_to_out_synchronizer 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_005|clock_xer 125 0 0 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_005 127 2 0 2 121 2 2 2 0 0 0 0 0
u0|mm_interconnect_0|crosser_004|clock_xer|out_to_in_synchronizer 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_004|clock_xer|in_to_out_synchronizer 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_004|clock_xer 125 0 0 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_004 127 2 0 2 121 2 2 2 0 0 0 0 0
u0|mm_interconnect_0|crosser_003|clock_xer|out_to_in_synchronizer 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_003|clock_xer|in_to_out_synchronizer 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_003|clock_xer 125 0 0 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_003 127 2 0 2 121 2 2 2 0 0 0 0 0
u0|mm_interconnect_0|crosser_002|clock_xer|out_to_in_synchronizer 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_002|clock_xer|in_to_out_synchronizer 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_002|clock_xer 125 0 0 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_002 127 2 0 2 121 2 2 2 0 0 0 0 0
u0|mm_interconnect_0|crosser_001|clock_xer|out_to_in_synchronizer 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_001|clock_xer|in_to_out_synchronizer 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_001|clock_xer 125 0 0 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser_001 127 2 0 2 121 2 2 2 0 0 0 0 0
u0|mm_interconnect_0|crosser|clock_xer|out_to_in_synchronizer 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser|clock_xer|in_to_out_synchronizer 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser|clock_xer 125 0 0 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|crosser 127 2 0 2 121 2 2 2 0 0 0 0 0
u0|mm_interconnect_0|sdram_s1_cmd_width_adapter 126 3 0 3 103 3 3 3 0 0 0 0 0
u0|mm_interconnect_0|sdram_s1_rsp_width_adapter|uncompressor 43 4 0 4 34 4 4 4 0 0 0 0 0
u0|mm_interconnect_0|sdram_s1_rsp_width_adapter 108 3 0 3 121 3 3 3 0 0 0 0 0
u0|mm_interconnect_0|rsp_mux_001|arb|adder 12 6 0 6 6 6 6 6 0 0 0 0 0
u0|mm_interconnect_0|rsp_mux_001|arb 7 0 4 0 3 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|rsp_mux_001 363 0 0 0 123 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|rsp_mux|arb|adder 48 24 0 24 24 24 24 24 0 0 0 0 0
u0|mm_interconnect_0|rsp_mux|arb 16 0 4 0 12 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|rsp_mux 1443 0 0 0 132 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_011 123 1 2 1 121 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_010 123 1 2 1 121 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_009 124 4 2 4 241 4 4 4 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_008 123 1 2 1 121 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_007 124 4 2 4 241 4 4 4 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_006 124 4 2 4 241 4 4 4 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_005 123 1 2 1 121 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_004 123 1 2 1 121 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_003 123 1 2 1 121 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_002 123 1 2 1 121 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux_001 123 1 2 1 121 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|rsp_demux 123 1 2 1 121 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_011 123 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_010 123 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_009|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_009|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_009 243 0 0 0 122 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_008 123 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_007|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_007|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_007 243 0 0 0 122 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_006|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_006|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_006 243 0 0 0 122 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_005 123 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_004 123 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_003 123 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_002 123 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux_001 123 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_mux 123 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|cmd_demux_001 125 9 2 9 361 9 9 9 0 0 0 0 0
u0|mm_interconnect_0|cmd_demux 134 144 2 144 1441 144 144 144 0 0 0 0 0
u0|mm_interconnect_0|sdram_s1_burst_adapter|altera_merlin_burst_adapter_uncompressed_only.burst_adapter 105 3 5 3 103 3 3 3 0 0 0 0 0
u0|mm_interconnect_0|sdram_s1_burst_adapter 105 0 0 0 103 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_013|the_default_decode 0 12 0 12 12 12 12 12 0 0 0 0 0
u0|mm_interconnect_0|router_013 111 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_012|the_default_decode 0 12 0 12 12 12 12 12 0 0 0 0 0
u0|mm_interconnect_0|router_012 111 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_011|the_default_decode 0 12 0 12 12 12 12 12 0 0 0 0 0
u0|mm_interconnect_0|router_011 93 0 2 0 103 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_010|the_default_decode 0 12 0 12 12 12 12 12 0 0 0 0 0
u0|mm_interconnect_0|router_010 111 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_009|the_default_decode 0 12 0 12 12 12 12 12 0 0 0 0 0
u0|mm_interconnect_0|router_009 111 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_008|the_default_decode 0 12 0 12 12 12 12 12 0 0 0 0 0
u0|mm_interconnect_0|router_008 111 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_007|the_default_decode 0 12 0 12 12 12 12 12 0 0 0 0 0
u0|mm_interconnect_0|router_007 111 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_006|the_default_decode 0 12 0 12 12 12 12 12 0 0 0 0 0
u0|mm_interconnect_0|router_006 111 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_005|the_default_decode 0 12 0 12 12 12 12 12 0 0 0 0 0
u0|mm_interconnect_0|router_005 111 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_004|the_default_decode 0 12 0 12 12 12 12 12 0 0 0 0 0
u0|mm_interconnect_0|router_004 111 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_003|the_default_decode 0 12 0 12 12 12 12 12 0 0 0 0 0
u0|mm_interconnect_0|router_003 111 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_002|the_default_decode 0 12 0 12 12 12 12 12 0 0 0 0 0
u0|mm_interconnect_0|router_002 111 0 2 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router_001|the_default_decode 0 16 0 16 16 16 16 16 0 0 0 0 0
u0|mm_interconnect_0|router_001 111 0 6 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|router|the_default_decode 0 16 0 16 16 16 16 16 0 0 0 0 0
u0|mm_interconnect_0|router 111 0 6 0 121 0 0 0 0 0 0 0 0
u0|mm_interconnect_0|uart_s1_agent_rsp_fifo 151 39 0 39 110 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|uart_s1_agent|uncompressor 43 1 0 1 41 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|uart_s1_agent 307 39 49 39 325 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|sys_clk_timer_s1_agent_rsp_fifo 151 39 0 39 110 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|sys_clk_timer_s1_agent|uncompressor 43 1 0 1 41 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|sys_clk_timer_s1_agent 307 39 49 39 325 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|sdram_s1_agent_rdata_fifo 63 41 0 41 20 41 41 41 0 0 0 0 0
u0|mm_interconnect_0|sdram_s1_agent_rsp_fifo 133 39 0 39 92 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|sdram_s1_agent|uncompressor 43 1 0 1 41 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|sdram_s1_agent 239 22 33 22 254 22 22 22 0 0 0 0 0
u0|mm_interconnect_0|sys_pll_pll_slave_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
u0|mm_interconnect_0|sys_pll_pll_slave_agent_rsp_fifo 151 39 0 39 110 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|sys_pll_pll_slave_agent|uncompressor 43 1 0 1 41 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|sys_pll_pll_slave_agent 307 39 49 39 325 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|epcs_epcs_control_port_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
u0|mm_interconnect_0|epcs_epcs_control_port_agent_rsp_fifo 151 39 0 39 110 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|epcs_epcs_control_port_agent|uncompressor 43 1 0 1 41 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|epcs_epcs_control_port_agent 307 39 49 39 325 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|cpu_debug_mem_slave_agent_rsp_fifo 151 39 0 39 110 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|cpu_debug_mem_slave_agent|uncompressor 43 1 0 1 41 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|cpu_debug_mem_slave_agent 307 39 49 39 325 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|sys_id_control_slave_agent_rsp_fifo 151 39 0 39 110 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|sys_id_control_slave_agent|uncompressor 43 1 0 1 41 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|sys_id_control_slave_agent 307 39 49 39 325 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|io_pio_avalon_parallel_port_slave_agent_rsp_fifo 151 39 0 39 110 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|io_pio_avalon_parallel_port_slave_agent|uncompressor 43 1 0 1 41 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|io_pio_avalon_parallel_port_slave_agent 307 39 49 39 325 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|switch_pio_avalon_parallel_port_slave_agent_rsp_fifo 151 39 0 39 110 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|switch_pio_avalon_parallel_port_slave_agent|uncompressor 43 1 0 1 41 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|switch_pio_avalon_parallel_port_slave_agent 307 39 49 39 325 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|button_pio_avalon_parallel_port_slave_agent_rsp_fifo 151 39 0 39 110 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|button_pio_avalon_parallel_port_slave_agent|uncompressor 43 1 0 1 41 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|button_pio_avalon_parallel_port_slave_agent 307 39 49 39 325 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|led_pio_avalon_parallel_port_slave_agent_rsp_fifo 151 39 0 39 110 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|led_pio_avalon_parallel_port_slave_agent|uncompressor 43 1 0 1 41 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|led_pio_avalon_parallel_port_slave_agent 307 39 49 39 325 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|jtag_avalon_jtag_slave_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
u0|mm_interconnect_0|jtag_avalon_jtag_slave_agent_rsp_fifo 151 39 0 39 110 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|jtag_avalon_jtag_slave_agent|uncompressor 43 1 0 1 41 1 1 1 0 0 0 0 0
u0|mm_interconnect_0|jtag_avalon_jtag_slave_agent 307 39 49 39 325 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|cpu_instruction_master_agent 193 39 89 39 143 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|cpu_data_master_agent 193 39 89 39 143 39 39 39 0 0 0 0 0
u0|mm_interconnect_0|uart_s1_translator 94 22 43 22 57 22 22 22 0 0 0 0 0
u0|mm_interconnect_0|sys_clk_timer_s1_translator 94 22 43 22 55 22 22 22 0 0 0 0 0
u0|mm_interconnect_0|sdram_s1_translator 75 4 3 4 63 4 4 4 0 0 0 0 0
u0|mm_interconnect_0|sys_pll_pll_slave_translator 110 6 25 6 70 6 6 6 0 0 0 0 0
u0|mm_interconnect_0|epcs_epcs_control_port_translator 110 6 18 6 78 6 6 6 0 0 0 0 0
u0|mm_interconnect_0|cpu_debug_mem_slave_translator 110 5 18 5 82 5 5 5 0 0 0 0 0
u0|mm_interconnect_0|sys_id_control_slave_translator 110 6 26 6 35 6 6 6 0 0 0 0 0
u0|mm_interconnect_0|io_pio_avalon_parallel_port_slave_translator 110 6 25 6 75 6 6 6 0 0 0 0 0
u0|mm_interconnect_0|switch_pio_avalon_parallel_port_slave_translator 110 6 25 6 75 6 6 6 0 0 0 0 0
u0|mm_interconnect_0|button_pio_avalon_parallel_port_slave_translator 110 6 25 6 75 6 6 6 0 0 0 0 0
u0|mm_interconnect_0|led_pio_avalon_parallel_port_slave_translator 110 6 25 6 75 6 6 6 0 0 0 0 0
u0|mm_interconnect_0|jtag_avalon_jtag_slave_translator 110 5 29 5 70 5 5 5 0 0 0 0 0
u0|mm_interconnect_0|cpu_instruction_master_translator 111 51 0 51 103 51 51 51 0 0 0 0 0
u0|mm_interconnect_0|cpu_data_master_translator 111 12 0 12 103 12 12 12 0 0 0 0 0
u0|mm_interconnect_0 440 0 0 0 484 0 0 0 0 0 0 0 0
u0|uart|the_niosII_uart_regs 41 10 6 10 41 10 10 10 0 0 0 0 0
u0|uart|the_niosII_uart_rx|the_niosII_uart_rx_stimulus_source 15 0 14 0 1 0 0 0 0 0 0 0 0
u0|uart|the_niosII_uart_rx 17 1 0 1 13 1 1 1 0 0 0 0 0
u0|uart|the_niosII_uart_tx 25 0 0 0 4 0 0 0 0 0 0 0 0
u0|uart 26 0 0 0 18 0 0 0 0 0 0 0 0
u0|sys_pll|sd1 3 1 0 1 6 1 1 1 0 0 0 0 0
u0|sys_pll|stdsync2|dffpipe3 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|sys_pll|stdsync2 3 0 0 0 1 0 0 0 0 0 0 0 0
u0|sys_pll 49 41 30 41 34 41 41 41 0 0 0 0 0
u0|sys_id 3 16 2 16 32 16 16 16 0 0 0 0 0
u0|sys_clk_timer 23 0 12 0 17 0 0 0 0 0 0 0 0
u0|sdram|the_niosII_sdram_input_efifo_module 47 0 0 0 47 0 0 0 0 0 0 0 0
u0|sdram 47 1 1 1 40 1 1 1 16 0 0 0 0
u0|jtag|the_niosII_jtag_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr 4 0 0 0 6 0 0 0 0 0 0 0 0
u0|jtag|the_niosII_jtag_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 6 0 0 0 0 0 0 0 0
u0|jtag|the_niosII_jtag_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram 24 0 0 0 8 0 0 0 0 0 0 0 0
u0|jtag|the_niosII_jtag_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 6 0 0 0 0 0 0 0 0
u0|jtag|the_niosII_jtag_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state 5 0 0 0 8 0 0 0 0 0 0 0 0
u0|jtag|the_niosII_jtag_scfifo_r|rfifo|auto_generated|dpfifo 13 0 0 0 16 0 0 0 0 0 0 0 0
u0|jtag|the_niosII_jtag_scfifo_r|rfifo|auto_generated 12 0 0 0 16 0 0 0 0 0 0 0 0
u0|jtag|the_niosII_jtag_scfifo_r 13 0 1 0 16 0 0 0 0 0 0 0 0
u0|jtag|the_niosII_jtag_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr 4 0 0 0 6 0 0 0 0 0 0 0 0
u0|jtag|the_niosII_jtag_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 6 0 0 0 0 0 0 0 0
u0|jtag|the_niosII_jtag_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram 24 0 0 0 8 0 0 0 0 0 0 0 0
u0|jtag|the_niosII_jtag_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 6 0 0 0 0 0 0 0 0
u0|jtag|the_niosII_jtag_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state 5 0 0 0 8 0 0 0 0 0 0 0 0
u0|jtag|the_niosII_jtag_scfifo_w|wfifo|auto_generated|dpfifo 13 0 0 0 16 0 0 0 0 0 0 0 0
u0|jtag|the_niosII_jtag_scfifo_w|wfifo|auto_generated 12 0 0 0 16 0 0 0 0 0 0 0 0
u0|jtag|the_niosII_jtag_scfifo_w 12 0 0 0 16 0 0 0 0 0 0 0 0
u0|jtag 38 10 23 10 34 10 10 10 0 0 0 0 0
u0|epcs|the_boot_copier_rom|auto_generated 10 0 0 0 32 0 0 0 0 0 0 0 0
u0|epcs|the_niosII_epcs_sub 25 0 0 0 23 0 0 0 0 0 0 0 0
u0|epcs 48 0 16 0 36 0 0 0 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_nios2_oci|the_niosII_cpu_cpu_debug_slave_wrapper|the_niosII_cpu_cpu_debug_slave_sysclk 43 0 0 0 48 0 0 0 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_nios2_oci|the_niosII_cpu_cpu_debug_slave_wrapper|the_niosII_cpu_cpu_debug_slave_tck 130 0 1 0 43 0 0 0 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_nios2_oci|the_niosII_cpu_cpu_debug_slave_wrapper 123 0 0 0 50 0 0 0 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_nios2_oci|the_niosII_cpu_cpu_nios2_ocimem|niosII_cpu_cpu_ociram_sp_ram|the_altsyncram|auto_generated 47 0 0 0 32 0 0 0 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_nios2_oci|the_niosII_cpu_cpu_nios2_ocimem|niosII_cpu_cpu_ociram_sp_ram 47 0 0 0 32 0 0 0 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_nios2_oci|the_niosII_cpu_cpu_nios2_ocimem 92 0 6 0 65 0 0 0 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_nios2_oci|the_niosII_cpu_cpu_nios2_avalon_reg 48 0 28 0 68 0 0 0 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_nios2_oci|the_niosII_cpu_cpu_nios2_oci_im 54 38 51 38 47 38 38 38 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_nios2_oci|the_niosII_cpu_cpu_nios2_oci_pib 0 36 0 36 36 36 36 36 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_nios2_oci|the_niosII_cpu_cpu_nios2_oci_fifo|the_niosII_cpu_cpu_nios2_oci_fifo_cnt_inc 5 0 0 0 5 0 0 0 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_nios2_oci|the_niosII_cpu_cpu_nios2_oci_fifo|the_niosII_cpu_cpu_nios2_oci_fifo_wrptr_inc 4 2 0 2 4 2 2 2 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_nios2_oci|the_niosII_cpu_cpu_nios2_oci_fifo|the_niosII_cpu_cpu_nios2_oci_compute_input_tm_cnt 3 0 0 0 2 0 0 0 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_nios2_oci|the_niosII_cpu_cpu_nios2_oci_fifo 115 0 65 0 36 0 0 0 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_nios2_oci|the_niosII_cpu_cpu_nios2_oci_dtrace|niosII_cpu_cpu_nios2_oci_trc_ctrl_td_mode 9 0 6 0 4 0 0 0 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_nios2_oci|the_niosII_cpu_cpu_nios2_oci_dtrace 112 0 101 0 72 0 0 0 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_nios2_oci|the_niosII_cpu_cpu_nios2_oci_itrace 24 53 24 53 53 53 53 53 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_nios2_oci|the_niosII_cpu_cpu_nios2_oci_dbrk 97 0 0 0 101 0 0 0 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_nios2_oci|the_niosII_cpu_cpu_nios2_oci_xbrk 63 5 60 5 6 5 5 5 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_nios2_oci|the_niosII_cpu_cpu_nios2_oci_break 51 36 6 36 71 36 36 36 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_nios2_oci|the_niosII_cpu_cpu_nios2_oci_debug 50 1 30 1 7 1 1 1 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_nios2_oci 174 0 0 0 69 0 0 0 0 0 0 0 0
u0|cpu|cpu|niosII_cpu_cpu_register_bank_b|the_altsyncram|auto_generated 44 0 0 0 32 0 0 0 0 0 0 0 0
u0|cpu|cpu|niosII_cpu_cpu_register_bank_b 44 0 0 0 32 0 0 0 0 0 0 0 0
u0|cpu|cpu|niosII_cpu_cpu_register_bank_a|the_altsyncram|auto_generated 44 0 0 0 32 0 0 0 0 0 0 0 0
u0|cpu|cpu|niosII_cpu_cpu_register_bank_a 44 0 0 0 32 0 0 0 0 0 0 0 0
u0|cpu|cpu|the_niosII_cpu_cpu_test_bench 315 3 281 3 33 3 3 3 0 0 0 0 0
u0|cpu|cpu 149 1 28 1 129 1 1 1 0 0 0 0 0
u0|cpu 149 0 0 0 128 0 0 0 0 0 0 0 0
u0|switch_pio 47 0 38 0 32 0 0 0 0 0 0 0 0
u0|led_pio 43 0 28 0 40 0 0 0 0 0 0 0 0
u0|io_pio 43 0 1 0 32 0 0 0 32 0 0 0 0
u0|button_pio 45 0 38 0 32 0 0 0 0 0 0 0 0
u0 10 1 0 1 35 1 1 1 48 0 0 0 0