#============================================================
# Build by Terasic System Builder
#============================================================

set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE22F17C6
set_global_assignment -name TOP_LEVEL_ENTITY "HDMI_TMDS"
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.1
set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:03:29 FEBRUARY 18,2014"
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6

#============================================================
# CLOCK
#============================================================
set_location_assignment PIN_R8 -to CLOCK_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50


#============================================================
# SW
#============================================================
set_location_assignment PIN_M1 -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_location_assignment PIN_T8 -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_location_assignment PIN_B9 -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_location_assignment PIN_M15 -to SW[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]


#============================================================
# End of pin assignments by Terasic System Builder
#============================================================


set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_G15 -to R
set_location_assignment PIN_C15 -to G
set_location_assignment PIN_F15 -to B
set_location_assignment PIN_L15 -to C
set_instance_assignment -name IO_STANDARD LVDS -to R
set_instance_assignment -name IO_STANDARD LVDS -to B
set_instance_assignment -name IO_STANDARD LVDS -to C
set_instance_assignment -name IO_STANDARD LVDS -to G
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_location_assignment PIN_G16 -to "R(n)"
set_location_assignment PIN_F16 -to "B(n)"
set_location_assignment PIN_C16 -to "G(n)"
set_instance_assignment -name IO_STANDARD LVDS -to "B(n)"
set_location_assignment PIN_L16 -to "C(n)"
set_global_assignment -name SEARCH_PATH Modules/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/ip/altera/common/ip_toolbench/v1.3.0/bin/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/ip/altera/common/ip_toolbench/v1.3.0/bin/util/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/ip/altera/common/lib/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/ip/altera/test_pattern_generator/lib/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/ip/altera/test_pattern_generator/lib/ip_toolbench/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/quartus/cusp/include/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/quartus/cusp/include/cusp/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/quartus/cusp/include/cusp/fuLib/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/quartus/cusp/include/cusp/simlib/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/quartus/cusp/synthinclude/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/quartus/cusp/synthinclude/stlport/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/quartus/cusp/synthinclude/stlport/config/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/quartus/cusp/synthinclude/stlport/stl/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/quartus/cusp/systemc/include/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/quartus/cusp/systemc/include/sysc/communication/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/quartus/cusp/systemc/include/sysc/datatypes/bit/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/quartus/cusp/systemc/include/sysc/datatypes/fx/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/quartus/cusp/systemc/include/sysc/datatypes/int/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/quartus/cusp/systemc/include/sysc/datatypes/misc/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/quartus/cusp/systemc/include/sysc/kernel/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/quartus/cusp/systemc/include/sysc/tracing/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/quartus/cusp/systemc/include/sysc/utils/ -tag from_archive
set_global_assignment -name SEARCH_PATH altera/11.0/quartus/libraries/vhdl/ieee/ -tag from_archive
set_global_assignment -name SEARCH_PATH break_out_game/ -tag from_archive
set_global_assignment -name SEARCH_PATH megafunctions/ -tag from_archive
set_global_assignment -name VERILOG_FILE break_out_game/signed_mult.v
set_global_assignment -name VERILOG_FILE break_out_game/pong_ladrillos.v
set_global_assignment -name VERILOG_FILE break_out_game/list_ch14_10_pong_top.v
set_global_assignment -name VERILOG_FILE break_out_game/list_ch14_09_timer.v
set_global_assignment -name VERILOG_FILE break_out_game/list_ch14_08_m100_counter.v
set_global_assignment -name VERILOG_FILE break_out_game/list_ch14_07_pong_graph.v
set_global_assignment -name VERILOG_FILE break_out_game/list_ch14_06_pong_text.v
set_global_assignment -name VERILOG_FILE break_out_game/list_ch14_04_text_screen_gen.v
set_global_assignment -name VERILOG_FILE break_out_game/list_ch14_03_font_test_top.v
set_global_assignment -name VERILOG_FILE break_out_game/list_ch14_02_font_test_gen.v
set_global_assignment -name VERILOG_FILE break_out_game/list_ch14_01_font_rom.v
set_global_assignment -name VERILOG_FILE break_out_game/list_ch13_08_dot_top.v
set_global_assignment -name VERILOG_FILE break_out_game/list_ch13_07_bitmap_gen.v
set_global_assignment -name VERILOG_FILE "break_out_game/list_ch13_05_ pong_graph_animate.v"
set_global_assignment -name VERILOG_FILE break_out_game/list_ch13_03_pong_graph_st.v
set_global_assignment -name VERILOG_FILE break_out_game/list_ch13_01_vga_sync.v
set_global_assignment -name VERILOG_FILE break_out_game/list_ch12_04_xilinx_dual_port_ram_sync.v
set_global_assignment -name VERILOG_FILE break_out_game/list_ch06_02_debounce.v
set_global_assignment -name VERILOG_FILE break_out_game/ladrillos.v
set_global_assignment -name VERILOG_FILE break_out_game/instae2.v
set_global_assignment -name VERILOG_FILE break_out_game/frecGen.v
set_global_assignment -name VERILOG_FILE break_out_game/doublesync.v
set_global_assignment -name VERILOG_FILE break_out_game/break_out_Game.v
set_global_assignment -name VERILOG_FILE break_out_game/avarage.v
set_global_assignment -name VHDL_FILE pll_tx_cyclone3_xga.vhd
set_global_assignment -name VHDL_FILE pll_tx_cyclone3_vga.vhd
set_global_assignment -name VHDL_FILE pll_tx_cyclone3_svga.vhd
set_global_assignment -name VHDL_FILE pll_tx_cyclone3_sd.vhd
set_global_assignment -name VHDL_FILE pll_tx_cyclone3_hd.vhd
set_global_assignment -name VERILOG_FILE Modules/encode.v
set_global_assignment -name VERILOG_FILE Modules/hdclrbar.v
set_global_assignment -name VERILOG_FILE Modules/timing.v
set_global_assignment -name SDC_FILE HDMI_TMDS.SDC
set_global_assignment -name QIP_FILE DDIO.qip
set_global_assignment -name VERILOG_FILE Modules/timing_generator.v
set_global_assignment -name QIP_FILE pll_video_1.qip
set_global_assignment -name QIP_FILE global_clk.qip
set_global_assignment -name QIP_FILE pll_video_2.qip
set_global_assignment -name QIP_FILE Modules/pll_video_3.qip
set_global_assignment -name QIP_FILE pll_hd.qip
set_global_assignment -name QIP_FILE pll_svga.qip
set_global_assignment -name QIP_FILE pll_vga.qip
set_global_assignment -name QIP_FILE pll_xga.qip
set_global_assignment -name VERILOG_FILE Modules/simple_serializer.v
set_global_assignment -name QIP_FILE pattern_generator.qip
set_global_assignment -name QIP_FILE pll_wxga.qip
set_global_assignment -name QIP_FILE pll_tx_cyclone4_wxga.qip
set_global_assignment -name QIP_FILE pll_wxga2.qip
set_global_assignment -name QIP_FILE pll_tx_cyclone4_wxga2.qip
set_global_assignment -name QIP_FILE pll_tx_cyclone4_hd_hd.qip
set_global_assignment -name QIP_FILE pll_hd_hd.qip
set_global_assignment -name QIP_FILE pll_tx_cyclone4_HDTV1080P.qip
set_global_assignment -name QIP_FILE pll_HDTV1080P.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top