`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: AdriZcorp
// Engineer: Holguer Andres Becerra
// 
// Create Date:    02:50:56 08/17/2009 
// Design Name:    Div_frec
// Module Name:    frecGen 
// Project Name:   Divisor de frecuencia
// Target Devices: CYCLONE IV E EPCE22F17C6
// Tool versions:  Quartus II 10.1
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
//Fout=Fin/(2*(IN+1))

module Div_freq(reset,clock,IN,OUT);
input clock,reset;
input [31:0]IN;
output OUT;
reg [31:0]conteo=32'd0;
reg out_tmp=1'b0;

always @(posedge clock, posedge reset)
begin
	if(reset)
	begin	
		conteo<=32'd0;
	end
	else
	begin
	if (conteo >=IN) conteo<= 0;
	else conteo <= conteo+1;
	end
end
always @(posedge clock, posedge reset)
begin
	if(reset)
	begin	
		out_tmp<=1'd0;
	end
	else
	begin
	if (conteo >=IN) out_tmp<=!out_tmp;
	else out_tmp <= out_tmp;
	end
end

assign OUT = out_tmp;

endmodule